Shared L1 Cache Architecture Between Multiple CPU Cores

A prior art disclosure describing a CPU cache architecture in which Level 1 (L1) cache is partitioned into a dedicated per-core region and a shared inter-core region, enabling direct data sharing at the L1 cache level. Conceived independently by the inventor on May 23, 2026.

Authors

Publication Details

Journal
Zenodo (CERN European Organization for Nuclear Research)
Published
2026-05-23
DOI
https://doi.org/10.5281/zenodo.20357077
Primary Topic
Parallel Computing and Optimization Techniques
Type
article
Field-Weighted Citation Impact
0.00
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article

Shared L1 Cache Architecture Between Multiple CPU Cores

Jagrav M vaghela
Zenodo (CERN European Organization for Nuclear Research)
Parallel Computing and Optimization Techniques
article

Shared L1 Cache Architecture Between Multiple CPU Cores

Jagrav M vaghela
article en

Abstract

A prior art disclosure describing a CPU cache architecture in which Level 1 (L1) cache is partitioned into a dedicated per-core region and a shared inter-core region, enabling direct data sharing at the L1 cache level. Conceived independently by the inventor on May 23, 2026.

Zenodo (CERN European Organization for Nuclear Research)
Openalex Percentile: Top 2%
Parallel Computing and Optimization Techniques
DOIOpen Access PDFOpenAlex
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