LE-Timing: Layout-Aware and Explainable Timing Prediction

Accurate and fast timing prediction at early design stages is crucial for achieving timing closure in very-large-scale integration (VLSI) design. Machine learning (ML) based approaches have been widely adopted for timing prediction to pursue both accuracy and speed. Unfortunately, these approaches fail to fully exploit the layout features which can significantly impact the timing metrics, thus leading to great accuracy degradation. In this paper, we propose LE-Timing, an end-to-end layout-aware timing prediction approach that can achieve better accuracy by leveraging important layout information. The key insight is that crucial information about coupling capacitance between routing wires can significantly impact timing metrics, and fully exploiting this layout information in the timing prediction model can substantially improve its accuracy. However, efficiently leveraging layout features while maintaining accuracy poses three key challenges: node-level layout-graph integration, domain experience utilization and training efficiency. To address these, we further propose three key technologies specially designed for LE-Timing correspondingly, including a layout-encoding net model, an explainable cell model, and an explicit-message-passing scheme. Experimental results on 16 open-source designs with an advanced 7-nm technology node demonstrate that LE-Timing achieves R 2 score 0.94 for arrival time prediction and lower error accumulation compared to the baselines.