CIM-AD: Hardware Efficient SRAM-based Computing in Memory Accelerator with Sparse Matrix in Diagonal Shift

Computing in memory requires more memory space to maintain its stability in hardware components. Due to instability and decreasing power supply voltages in Static Random-Access Memory (SRAM), cell reliability has become a major concern in terms of memory performance and power consumption. Traditionally, SRAM cell size has occupied more memory and consumed more power. To overcome this, a novel Compute in Memory Accelerator with Diagonal shift (CIM-AD) is proposed to reduce memory space and power consumption. The proposed 10-Transistor 2-Capacitor (10T2C) cell is designed for an SRAM array. The proposed 10T2C cell in CIM-AD reduces the memory usage by using a diagonal shift with the sparse method. Diagonal shift is used in the SRAM cell to perform weights in the convolutional layer. To reduce the zero weights in the diagonal shift, a sparse matrix is used. Finally, the memory usage is reduced by using the proposed CIM-AD. The proposed CIM-AD provides high performance in the CIFAR-10 dataset images with lower power consumption. The proposed CIM-AD performance improve throughput, and reduces static power. The proposed SRAM 10T2C cell in the SRAM array keeps data performance high in application requirements. The proposed design achieves better performance by reducing memory usage by 6.25% and power consumption by 52.26%. Further, the proposed CIM-AD in the CIFAR-10 dataset reveals an accuracy of 92.67%.