TAS: Adaptive Trace Sampling using Cache-Resident Exponentially Decaying Sketches

Distributed tracing systems often rely on uniform head sampling, which is inexpensive but value-blind, or tail sampling, which improves anomaly capture but requires centralized buffering. We present Threshold-Aware Sampling (TAS), a cache-resident edge sampler that maintains a recency-weighted latency baseline per service using a fixed-size Exponentially Decaying Sketch (EDS). TAS promotes spans whose latency exceeds a service-specific baseline by a configurable factor β, enabling value-aware sampling without centralized trace buffering. On Intel Sapphire Rapids, TAS achieves 15.67 M sampling decisions/s with 99.98% recall and 0.0061% false promotion rate on log-normal Zipfian workloads, using a 64KB sketch that fits within the processor's L1 data cache.

Authors

Publication Details

Journal
Zenodo (CERN European Organization for Nuclear Research)
Published
2026-05-22
DOI
https://doi.org/10.5281/zenodo.20337622
Primary Topic
Software System Performance and Reliability
Type
preprint
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preprint

TAS: Adaptive Trace Sampling using Cache-Resident Exponentially Decaying Sketches

Ankit Toshniwal
Zenodo (CERN European Organization for Nuclear Research)
Software System Performance and Reliability
preprint

TAS: Adaptive Trace Sampling using Cache-Resident Exponentially Decaying Sketches

Ankit Toshniwal
preprint en

Abstract

Distributed tracing systems often rely on uniform head sampling, which is inexpensive but value-blind, or tail sampling, which improves anomaly capture but requires centralized buffering. We present Threshold-Aware Sampling (TAS), a cache-resident edge sampler that maintains a recency-weighted latency baseline per service using a fixed-size Exponentially Decaying Sketch (EDS). TAS promotes spans whose latency exceeds a service-specific baseline by a configurable factor β, enabling value-aware sampling without centralized trace buffering. On Intel Sapphire Rapids, TAS achieves 15.67 M sampling decisions/s with 99.98% recall and 0.0061% false promotion rate on log-normal Zipfian workloads, using a 64KB sketch that fits within the processor's L1 data cache.

Zenodo (CERN European Organization for Nuclear Research)
Software System Performance and Reliability
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