Trainable neuromorphic spintronic hardware Via analog finite-difference gradient methods

Spintronic nano-neurons offer a promising route towards energy-efficient, high performance hardware neural networks thanks to their inherent low-input nonlinear dynamics. However, training such networks remains a major bottleneck as it depends on oversimplified models of device behaviour and is highly sensitive to device variability. Here, we introduce a hardware architecture that overcomes these limitations by enabling on-device generation of gradients. First, we introduce theoretically and demonstrate experimentally that magnetic tunnel junctions can generate tunable and complex nonlinear responses. Building on this, we implement an analogue finite-difference approach to enable on-chip training in spintronic neural networks with one and two hidden layers. We experimentally implemented device-in-the-loop backpropagation in a magnetic tunnel junction–based neural network, achieving a classification accuracy of 93.3% despite pronounced device variability. During training, the gradients generated by the proposed analog neurons closely match the values derived numerically, without incurring in computational overhead. Via physical simulations, we also demonstrate that this approach can be scaled up to support training in deep architectures. Our results pave the way for reliable, trainable and fully analogue spintronic neural networks, opening up new possibilities for next-generation, energy-efficient artificial intelligence hardware. Spintronic in-hardware training has relied on software-based gradient calculations or unsupervised methods, leading to substantial computational overhead. Pereira et al. propose an MTJ-based analog neuron and hardware architecture that enables on-chip neuromorphic training without digital models, achieving high classification accuracy.