Toward Enhanced Hardware IP Security: Community Evaluation of Logic Locking, State Space Transformation, Redaction, and NoC Routing Table Configuration

As global hardware manufacturing expands and the need to meet time-to-market demands grows, companies increasingly depend on the zero-trust model to manage most of the design process for Integrated Circuits (ICs). Consequently, valuable hardware intellectual property (IP) becomes vulnerable to piracy, cloning, reverse engineering (RE), and unauthorized modifications throughout the global IC supply chain. Current security solutions are designed to safeguard the designs and protect sensitive information throughout the design flow. In this study, we present a thorough evaluation of various IP countermeasure techniques, including Logic Locking, State Space Transformation, Fine-grain Hardware Redaction, and NoC Routing Table Configuration, described in the existing literature. Inspired by cybersecurity competitions and community evaluation efforts, we designed a collaborative benchmarking initiative to evaluate these techniques on open-source benchmark designs, unveil the gaps and limitations of each technique, and discover crucial paths for future exploration. Through a retrospective analysis of this initiative, the insights we gained can significantly contribute to improving countermeasure techniques in the broad domain of hardware security and trust.