An FPGA-Based Event-Timing Front-End for Time-Resolved Sensing with Dual-Mode Experimental Characterization

This work presents an FPGA-based edge-event timing front-end for time-resolved sensing and event-driven measurement scenarios. The proposed design is intended as a detector-independent timing subsystem whose architectural choices are motivated by constraints that are common in single-photon avalanche diode (SPAD)-based and other asynchronous time-resolved sensing workflows, including event trustworthiness, dead-time sensitivity, and constrained downstream readout. Rather than treating the implementation as an isolated interpolation macro, this work evaluates it as an experimentally observable timing subsystem that combines carry-chain-based fine interpolation, coarse–fine timestamp formation, explicit event-quality assessment, dead-time-aware handling, and lightweight host-visible export. The experimental validation is organized around two complementary modes. An internal ILA-based mode is used to verify coherent front-end behavior under MHz-range short-pulse excitation, while a UART-based campaign identifies practical host-visible operating regions through baseline, repeatability, pulse-width, safe-versus-aggressive, and intermediate frequency-sweep experiments. The results identify a safe export-compatible operating point, a more exploratory high-rate regime, and an experimentally interpretable transition between them that, while not strictly monotonic in all metrics, does not exhibit catastrophic degradation across the explored frequency range. Taken together, the measurements indicate that the proposed architecture is best understood not as a best-case standalone time-to-digital (TDC) benchmark but as an experimentally characterized timing front-end whose practical behavior can be interpreted across complementary internal and export-visible operating regimes.