Generalized Positive/Negative Floating Impedance Multiplier Circuit and Its Application

Passive components in integrated circuits occupy significant areas and increase production costs, driving the demand for compact alternatives. This study presents a generalized, electronically controllable positive/negative floating impedance multiplier implemented in TSMC 180 nm CMOS technology. To achieve a compact layout, the architecture utilizes custom-designed operational transconductance amplifiers (OTAs). The circuit operates on a lossless principle, scaling resistance, capacitance, and inductance values within a wide multiplication range of −100 to +100 using only a single base element. Comprehensive LTspice simulations including PVT, Monte Carlo, THD, and noise analyses verify the design’s stable operation, low distortion, and favorable noise characteristics across various filter configurations. Furthermore, practical feasibility is validated through SPICE simulations using commercial LM13700 OTA, confirming consistent behavior for real-world applications. The proposed active topology occupies a compact core area of only 5831 μm2. By scaling down large passive components, this design decreases the overall system-level footprint, providing a versatile and area-efficient solution for tunable analog IC applications. It should be noted that the reported 5831 μm2 corresponds to the active core only, while the effective system-level area benefit depends on the selected base impedance and the target application.