Quantifying Scalability-Performance Trade-offs: A Design Space Exploration of Compute-in-Memory based Ising Machines

Ising machines offer a promising paradigm for solving NP-hard combinatorial optimization problems (COPs). Among various approaches, Compute-in-Memory (CIM) based Ising machines show superior performance due to the reduced data transfer and efficient Multiply-and-Accumulate (MAC) operation. However, the scalability of CIM-based implementations remains limited due to challenges including restricted mapping size, circuit limitations and device non-idealities especially with emerging non-volatile memory (eNVM) technologies. This work presents a comprehensive design space exploration of three scalable CIM architectures for fully connected Ising models, analyzing their performance under constraints such as IR-drop, device variation, parasitic capacitance and analog to digital converter (ADC) precision loss across different memory technologies. According to our evaluation for randomized MAX-CUT benchmarks, the properly chosen design (Single array XNOR-based CIM mapping with Current Sense Amplifier) maintained over 95% solution quality while achieving nearly 2 × higher energy efficiency and a 40% area reduction for 128-spins Ising model, while the optimal solution (Distributed subarray computation with 1-bit ADC precision loss) improves energy efficiency by 2.1 × with small solution quality degradation ( \(\sim 10\% \) ) for large-scale models (1024 spins) compared to other designs options.