RISC-V Instruction Fetch Architecture Optimized for Harsh Environments

Abstract An increasing number of sensors and actuators are being used in today’s high-tech drilling tools to further optimize the drilling process. Each sensor and actuator either generates data that needs to be processed or requires real-time input control signals. RISC-V processors are being developed to meet the computational demands of today’s applications. A known bottleneck for processors is the data flow and instruction input to the processor, especially as memory response times are particularly high for the state-of-the-art harsh environment silicon-on-insulator (SOI) technology. This paper presents a high-performance instruction fetch architecture that achieves a high clock frequency while preserving high instructions per cycle. We evaluate different approaches implementing and propose a design that is able to reach up to 0.8 instruction per cycle (IPC) with a clock frequency of 181 MHz, which is more than twice as high as previous designs in this technology. This design is first tested in isolation an then combined with our current RISC-V processor specially designed to be used in such a harsh environment. This architecture achieves 146.5 million instructions per second (MIPS), which is four times higher than other off the shelf solution synthesized for the same harsh environment technology.