Quantitative Evaluation of Fault Detection Strategies in FPGAs for Space Applications

Abstract Field-programmable gate arrays (FPGAs) in space applications come with the drawback of radiation effects. This also applies to the electronics of the Bose Einstein Condensate and Cold Atom Laboratory (BECCAL) apparatus, which will operate on the International Space Station (ISS) for several years. A total of more than 100 FPGAs distributed throughout the setup will be used for high-precision control of specialized sensors and actuators at nanosecond scale. On ISS, radiation effects must be taken into account, the functionality of the electronics must be monitored, and errors must be handled properly. Commercial off-the-shelf (COTS) FPGAs are used, which are not radiation hardened by design. This paper describes the methods and measures used to mitigate the effects of radiation in an application specific COTS-FPGA-based communication network. Based on the firmware for a central communication network switch in BECCAL the steps are described to integrate fault mitigation into the design while optimizing the firmware to stay within the (FPGAs) tight resource constraints. Multiple different redundancy mechanisms are implemented, using VHDL constructs or the Synplify Elite synthesis tool, to select the variant fitting the task best. A redundant integrity checker module is developed that can notify preceding network devices of data and configuration bit errors. The firmware is validated and evaluated by injecting faults into data and configuration registers in simulation and real hardware. For the switch fabric it is shown, that dual modular redundancy (DMR) with error detection is the best strategy for BECCAL. Together with the triple modular redundancy (TMR) protected integrity checker, this combination completely prevents silent data corruptions (SDCs) in the design as shown in simulation and by injecting faults into hardware using the Intel Fault Injection FPGA IP Core while staying within the resource limitation of a low-cost COTS FPGA.