ITU and Semiconductors: A Single-Axiom Foundation for Devices, Scaling, Beyond-CMOS, and the 2026-2040 Roadmap

We apply the Information-Theoretic Unification (ITU) framework (Terada 2026, DOI 10.5281/zenodo.20109210) to semiconductor transistors. The single ITU axiom dS = d<K> governs the Landauer minimum bit-erasure energy, the Boltzmann subthreshold-swing tyranny, the 3D scaling progression (FinFET -> GAAFET -> CFET), and the beyond-CMOS device landscape. This is Tier 1 paper #4, completing the ITU engineering rectangle: Quantum Computing (Tier 1 #1, DOI 10.5281/zenodo.20139391) + Machine Consciousness / ASI (#2, DOI 10.5281/zenodo.20150501) + Cryptography (#3, DOI 10.5281/zenodo.20151059) + Semiconductors (this paper) as physical substrate. Phase 55: ITU foundation. Landauer k_B T ln 2 limit (17.9 meV at 300 K) and 60 mV/decade Boltzmann tyranny shown as thermal-K_A consequences. Moore + Koomey trends leave ~2.5 decades of improvement before Landauer limit. Phase 56: FinFET -> GAAFET -> CFET as ITU eta-maximisation (gate coupling area per channel volume). WKB tunneling ends classical MOSFET below 1 nm. Sharvin contact resistance quantises at h/(2e^2) = 12.9 kOhm below 25 nm^2. Phase 57: Eight beyond-CMOS device classes benchmarked on a unified ITU figure-of-merit. Photonic computing wins with FoM ~17,500x CMOS, driven by h*nu >> k_B T non-thermal K_A. Heterogeneous SoCs dominate the 2030s. Phase 58: 2026-2040 industry roadmap. Logistic adoption for seven beyond-CMOS technologies. Process node floor ~0.5 nm. Semiconductor TAM reaches $1 trillion by 2030, $2 trillion by 2040. Taiwan share drops 55% -> 36% through geopolitical diversification. 10 falsifiable predictions issued. Central thesis: under ITU, the transistor is a 1-bit QECC against k_B T noise; 3D wrapping reflects K_A area maximisation; beyond-CMOS winners require non-thermal K_A. Honest framing: this is a Pass-1 interpretive paper reframing known semiconductor physics within ITU; novel predictions distinguishing ITU from standard physics await Pass-2 work. Includes 4 theory documents, 4 Python numerical experiments, 4 figures, 4 JSON summaries. Total runtime ~30 seconds.

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Publication Details

Journal
Zenodo (CERN European Organization for Nuclear Research)
Published
2026-05-14
DOI
https://doi.org/10.5281/zenodo.20174036
Primary Topic
Advancements in Semiconductor Devices and Circuit Design
Type
preprint
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preprint

ITU and Semiconductors: A Single-Axiom Foundation for Devices, Scaling, Beyond-CMOS, and the 2026-2040 Roadmap

Munehiro Terada
Zenodo (CERN European Organization for Nuclear Research)
Advancements in Semiconductor Devices and Circuit Design
preprint

ITU and Semiconductors: A Single-Axiom Foundation for Devices, Scaling, Beyond-CMOS, and the 2026-2040 Roadmap

Munehiro Terada
preprint en

Abstract

We apply the Information-Theoretic Unification (ITU) framework (Terada 2026, DOI 10.5281/zenodo.20109210) to semiconductor transistors. The single ITU axiom dS = d<K> governs the Landauer minimum bit-erasure energy, the Boltzmann subthreshold-swing tyranny, the 3D scaling progression (FinFET -> GAAFET -> CFET), and the beyond-CMOS device landscape. This is Tier 1 paper #4, completing the ITU engineering rectangle: Quantum Computing (Tier 1 #1, DOI 10.5281/zenodo.20139391) + Machine Consciousness / ASI (#2, DOI 10.5281/zenodo.20150501) + Cryptography (#3, DOI 10.5281/zenodo.20151059) + Semiconductors (this paper) as physical substrate. Phase 55: ITU foundation. Landauer k_B T ln 2 limit (17.9 meV at 300 K) and 60 mV/decade Boltzmann tyranny shown as thermal-K_A consequences. Moore + Koomey trends leave ~2.5 decades of improvement before Landauer limit. Phase 56: FinFET -> GAAFET -> CFET as ITU eta-maximisation (gate coupling area per channel volume). WKB tunneling ends classical MOSFET below 1 nm. Sharvin contact resistance quantises at h/(2e^2) = 12.9 kOhm below 25 nm^2. Phase 57: Eight beyond-CMOS device classes benchmarked on a unified ITU figure-of-merit. Photonic computing wins with FoM ~17,500x CMOS, driven by h*nu >> k_B T non-thermal K_A. Heterogeneous SoCs dominate the 2030s. Phase 58: 2026-2040 industry roadmap. Logistic adoption for seven beyond-CMOS technologies. Process node floor ~0.5 nm. Semiconductor TAM reaches $1 trillion by 2030, $2 trillion by 2040. Taiwan share drops 55% -> 36% through geopolitical diversification. 10 falsifiable predictions issued. Central thesis: under ITU, the transistor is a 1-bit QECC against k_B T noise; 3D wrapping reflects K_A area maximisation; beyond-CMOS winners require non-thermal K_A. Honest framing: this is a Pass-1 interpretive paper reframing known semiconductor physics within ITU; novel predictions distinguishing ITU from standard physics await Pass-2 work. Includes 4 theory documents, 4 Python numerical experiments, 4 figures, 4 JSON summaries. Total runtime ~30 seconds.

Zenodo (CERN European Organization for Nuclear Research)
Stroke Association (GB)
Industry, innovation and infrastructure
Advancements in Semiconductor Devices and Circuit Design
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