Wafer Defect Classification Method Based on Improved EfficientNet Model

To address the accuracy limitations in identifying micro-scale and low-distinguishability defects, we proposes an improved EfficientNet model for wafer defect classification in semiconductor fabrication. In particular, we construct the model using EfficientNetV2 architectures as the backbone and introduce a multi-scale self-attention enhancement module to strengthen the capture capability for critical defect characteristics. This module consists of four parallel self-attention enhancement modules, aiming to obtain spatial context information at different levels and enhance relevant features through a self-attention mechanism. Meanwhile, we merge the manually extracted features of defects with the CNN’s fully connected layer, effectively compensating for the deficiency of automatic features in the differentiated representation of defects. The manual feature extraction module leverages image processing techniques to capture diverse morphological characteristics of defects including geometric features, moment features and texture features. We simulate and generate a lithography SEM image dataset with various types of defects based on the typical line-space structure and the ICCAD2019 mask pattern dataset. The total sample size of the wafer defect dataset is 1500, covering 15 typical defects with an average distribution. The classification performance of models is evaluated on the simulated defect dataset. The results indicate that the overall classification accuracy of the improved model reaches 96.60%, representing an improvement of 8.14% compared to the original EfficientNetV2. This demonstrates the superiority of the proposed model in addressing classification tasks involving micro-scale and low-distinguishability defects.