Impact of Surface Treatment on Noise in PL Measurements of Silicon Vacancies in 4H-SiC Lateral PIN-Diodes
environment. Single emitters in these PIN-diodes show an increased signal-to-noise ratio of 15 for near-surface and 50 for deeper emitters on both c-plane and a-plane wafers.
Authors
- Susanne Beuer (ORCID: https://orcid.org/0009-0009-2485-4725)
- Christian Miersch (ORCID: https://orcid.org/0009-0006-7534-6649)
- Alexander May (ORCID: https://orcid.org/0000-0001-8714-5840)
- Jannik H. Schwarberg (ORCID: https://orcid.org/0000-0002-8977-4517)
- Mathias Rommel (ORCID: https://orcid.org/0000-0002-1141-3228)
- Wolfgang Knolle (ORCID: https://orcid.org/0000-0003-4455-6898)
- Christian Gobert
- Jörg Schulze (ORCID: https://orcid.org/0000-0003-3621-7888)
- Chihang Luo
- Fabian Magerl
- Martin Siebert
- Franziska C. Beyer (ORCID: https://orcid.org/0000-0002-1727-7511)
- Jan F. Dick
- Heino Möller
Institutions
- University of Science and Technology of China (CN)
- Friedrich-Alexander-Universität Erlangen-Nürnberg (DE)
- Advanced Materials and Devices (United States) (US)
- Intego (Germany) (DE)
- Fraunhofer Institute for Integrated Systems and Device Technology (DE)
- Leibniz Institute of Surface Engineering (DE)
Publication Details
- Journal
- Nano Letters
- Published
- 2026-05-12
- DOI
- https://doi.org/10.1021/acs.nanolett.6c00646
- Primary Topic
- Silicon Carbide Semiconductor Technologies
- Type
- article
- Field-Weighted Citation Impact
- 0.00
Funders
- Deutsche Forschungsgemeinschaft
- Chinesisch-Deutsche Zentrum für Wissenschaftsförderung