An Efficient Quantum-Dot Cellular Automata Memory Architecture for Internet of Things Systems

Internet of Things (IoT) nodes continuously acquire, buffer, and transmit sensor data under strict constraints on area, latency, and energy consumption. However, conventional complementary metal–oxide–semiconductor (CMOS)-based memory-access circuits face increasing power loss, parasitic effects, interconnect complexity, and sensitivity to process variations at the nanoscale. To address these limitations, this paper proposes a quantum-dot cellular automata (QCA)-based decoder-driven static random-access memory (SRAM)-access architecture for compact and energy-efficient IoT perception-layer memory. The proposed framework integrates three main components: a majority-logic RAM cell with feedback-based storage and non-destructive readout, a compact 2 × 4 decoder with enable and auxiliary asynchronous set/reset control, and a 1 × 4 SRAM array in which the decoder is embedded to reduce routing and clocking overhead. The circuit layouts were implemented and functionally verified using QCADesigner 2.0.3, while the energy behavior was evaluated using QCADesigner-E. Simulation results confirm correct write/read (W/R) and address-selection behavior. The proposed 2 × 4 decoder achieves 86 QCA cells, 0.08 µm2 occupied area, and one clocking unit, reducing cell count, area, and clocking by 48.19%, 50.00%, and 20.00%, respectively, compared with the best selected decoder baseline. The integrated 1 × 4 SRAM array achieves 684 cells and 14 clocking units, improving timing by 30.00% compared with the closest SRAM-array baseline. These results demonstrate that the proposed QCA-based memory-access structure provides a compact and low-overhead solution for energy-constrained IoT communication systems.