Execution-Time Phase Exposure in Quantum Circuits: A Missing Diagnostic Layer for Coherence-Relevant Idle Time

This whitepaper identifies execution-time phase exposure as a missing diagnostic layer in quantum circuit evaluation. Quantum circuit performance is commonly evaluated through aggregate quantities such as gate count, circuit depth, total idle time, calibration data, error rates, and hardware coherence parameters such as T1 and T2. These quantities are necessary, but they do not identify when a qubit is actually carrying phase-sensitive quantum information whose preservation matters to the intended readout. The central observation is that idle time is not uniformly harmful. Idle time becomes consequential when it overlaps an active phase-bearing execution window: an interval in which phase-sensitive structure exists, persists, and remains relevant to a later readout. The whitepaper frames this distinction from a compact-fiber readout perspective and reports sanitized aggregate validation results from contemporary superconducting quantum hardware. The validation supports the claim that circuits with similar aggregate metrics can differ in observed performance because their idle intervals occur in different execution-time locations relative to phase-bearing structure. This record contains the whitepaper PDF only. It does not include circuit definitions, job identifiers, report schemas, implementation details, raw validation artifacts, or non-public workflow material.