CHARIOT: A Communication-Aware Exploration Framework for 2.5D/3D Silicon Interposer Design

Interposer design is crucial for optimizing inter-chiplet communication efficiency, performance, and energy consumption in 2.5D/3D integrated systems. To facilitate performance analysis and design space exploration (DSE) of interposers, this work presents CHARIOT, a fast, comprehensive exploration framework that establishes a systematic methodology for analyzing and exploring the design space of both passive and active interposers’ architecture. The design space of interposers is first developed to evaluate system performance. Then a roofline model-based methodology is introduced to analyze the bottleneck of performance. A multi-objective Bayesian optimization-based DSE framework, CHARIOT, is proposed, featuring a scheduling engine tailored to different interposer types and a communication-aware exploration engine for coordinated multi-objective exploration of the design space. Compared to the state-of-the-art (SOTA) chiplet system, the CHARIOT-generated optimal passive and active interposer designs achieve energy efficiency improvement up to 1.33x and 1.96x, as well as performance gains up to 1.49x and 1.75x speed-up. The Pareto frontiers of competitive design choices enable selecting the most suitable option based on the designers’ requirements.