Investigating the performance and prediction of junctionless FET using Artificial Neural Network (ANN) model

This work presents device-to-modelling investigation of a 20 nm double-gate junctionless field-effect transistor (DG-JLFET) with high-k dielectric engineering and artificial neural network (ANN)-based performance prediction. A calibrated TCAD framework is done to compare HfO2, Si3N4, and SiO2 gate dielectrics under same structural conditions, alongside a conventional junction-based MOSFET. The results shows that the DG-JLFET with HfO2 achieves better electrostatic integrity, reduced subthreshold slope of ~ 60 mV/dec, low drain-induced barrier lowering of ~ 25 mV/V and an enhanced ON/OFF current ratio exceeding 1011-1012. Compared to SiO2 and Si3N4, the high-k dielectric strengthens gate-channel coupling, suppresses short-channel effects and improves threshold voltage control at the 20 nm technology node. Transconductance analysis confirms stable charge modulation with minimized mobility degradation, while temperature and doping studies shows predictable bulk conduction behaviour characteristic of junctionless architectures. To accelerate design exploration, a multilayer ANN model is developed and trained using TCAD-generated datasets to predict key electrical parameters including threshold voltage, subthreshold slope and DIBL. The ANN achieves prediction accuracies above 95% for Vth and ~ 99% for SS and DIBL with transfer characteristics matching simulated results across the operating range. Circuit-level validation using a resistive-load inverter further confirms the practical applicability of the proposed device. The combined TCAD-ANN framework shows that HfO2-based DG-JLFETs offer an optimized balance between drive current, leakage suppression, and electrostatic robustness, providing a solution for low-power logic.