High-performance FPGA implementation of HEVC with dynamic programming for optimized intra-frame prediction

High-efficiency video coding (HEVC) is renowned for achieving efficient video compression without compromising quality; however, it introduces significant computational complexity, particularly in intra-frame prediction. This paper proposes a dynamic programming optimization technique for HEVC encoders, implemented on an FPGA platform to improve both performance and resource efficiency. The architecture, which includes a sample extractor, correlation analyser, and sample predictor, uses dynamic programming to compute optimal pixel correlations and generate precise directional vectors, enhancing prediction accuracy. Hardware validation was performed on the Virtex-6 ML605 FPGA platform, achieving an operating frequency of 838 MHz and enabling real-time encoding of Ultra High Definition (UHD) 4K video frames. Benchmark results show that the proposed design achieves a 43% improvement in throughput, processing 50 frames per second at UHD resolution, compared with existing HEVC implementations. The architecture demonstrates high resource efficiency, utilising only 12% of available logic, 7% of block RAM, and 4% of DSP resources, while maintaining low power consumption (2.4 W). PSNR comparisons against traditional discrete cosine transform (DCT)-based prediction methods show consistent improvements in video quality, ranging from [Formula: see text] dB to [Formula: see text] dB across various block sizes (4 × 4, 8 × 8, 16 × 16, and 32 × 32). The proposed architecture minimises encoding time and achieves low latency, making it well suited to real-time applications. The proposed method can facilitate efficient, high-quality video compression in next-generation video processing systems deployed on FPGA platforms.