A Test Architecture for Bundled-Data Asynchronous NoC Switches Using Commercial ATPG Tools

Asynchronous Networks-on-Chip (NoCs) offer significant benefits in energy efficiency, area, and modularity, but their lack of compatibility with standard production test flows hinders industrial adoption. This paper demonstrates that a stateof- the-art 2-phase bundled-data asynchronous NoC (TaBuLA) can be transformed and made fully compliant with standard scanbased testing, enabling direct use of unmodified industrial ATPG tools and conventional ATE. Each asynchronous switch component is converted into a synchronous testable abstraction, addressing latch- and FF-related issues and meeting full controllability and observability requirements. As a result, a high-quality stuck-at<br/>fault coverage of 96.53% is achieved with a marginal 2% I/O pin count overhead. The unoptimized area, performance and power overheads (2.6x, 1.9x and at most 2x, respectively) achieve a more balanced trade-off between cost-coverage-industrial compliance than previous custom DFT infrastructures for asynchronous NoCs.