NOCTOPUS: Network-on-Chip topology optimization and prediction using simulation-data

Abstract Designing optimal Network-on-Chip (NoC) architectures remains a complex challenge due to architectural intricacies and the high cost of simulation-based performance evaluation. This work presents NOCTOPUS, a novel framework that predicts optimal NoC configurations using System-on-Chip (SoC) parameters and performance metrics. At its core, NOCTOPUS is a pipelined Graph Neural Network (GNN) architecture, enhanced by human-in-the-loop learning to guide graph structure construction. A cycle-accurate NoC simulator generates a rich dataset via Latin Hypercube Sampling, enabling robust training and evaluation. Experimental results show that the proposed approach significantly outperforms traditional simulation methods in both accuracy and computational efficiency. Future directions include integrating deeper design knowledge and extending applicability to diverse SoC fabrics.