Design and Performance Investigation of a Dual p-GaN Recessed Gate High Electron Mobility Transistors for High Threshold Voltage Applications

In this paper, a normally off high-electron-mobility transistor (HEMT) incorporating a recessed p-GaN gate and a buried p-GaN region is proposed and investigated using Silvaco TCAD simulations. The two p-GaN regions located above and below the channel enhance the depletion of the two-dimensional electron gas (2DEG) in the channel, resulting in a threshold voltage (Vth) of 4.5 V. In the ON state, effective electrostatic modulation and improved gate control over the channel enable a drain current (Id) of 1 A/mm and transconductance (gm) of 443 mS/mm, demonstrating competitive performance compared to recently reported enhancement-mode (e-mode) HEMTs. The device exhibits a low ON-resistance (Ron) of 5.1 Ω.mm and a low sub-threshold swing (SS) of 78 mV/dec, indicating favorable performance for power electronics and radio-frequency (RF) switching applications. Moreover, the proposed HEMT employs a highly resistive buffer layer, which effectively reduces the leakage current components and improves the ON-OFF current ratio (Ion/Ioff). Overall, the proposed HEMT structure demonstrates an improved Vth–Id trade-off compared to several recently reported enhancement-mode HEMT designs.