Analytical Modeling and Extraction of Small Signal Model Parameters of Cylindrical Gate Stack ( <scp> HfO ₂ </scp> ) Silicon‐On‐Insulator Schottky Barrier <scp>MOSFET</scp> for High Frequency Circuits

ABSTRACT Small‐signal model of a MOSFET is an equivalent circuit that represents its electrical components and specifies the device's electrical characteristics. The non‐quasi‐static (NQS) model is among the most precise small‐signal models utilized in the design of analog and RF circuits. This work introduces an innovative device design known as Gate Stack Silicon on Insulator Schottky Barrier (GS‐SOISB CGAA) cylindrical MOSFET and analog/RF characteristics are extracted utilizing the Silvaco 3D device simulator. An analytical model of GS‐SOISB CGAA is also introduced and validated against the simulation findings. The NQS model of the GS‐SOISB cylindrical MOSFET is formulated to ascertain the extrinsic and intrinsic parasitic components utilizing Y ‐parameters in both the on and off states, respectively. The analog/RF characteristics and NQS model parameters of the GS‐SOISB cylindrical MOSFET have been compared with those of the SOISB cylindrical MOSFET and the SB cylindrical MOSFET. The revolutionary device has a lower gate‐source capacitance ( C GS ) of 7.95% and 8.79%, a gate‐drain capacitance ( C GD ) of 7.22% and 4.57%, and an overall gate capacitance ( C GG ) of 7.91% and 8% than SB and SOISB cylindrical MOSFETs. Compared to conventional SB cylindrical and SOISB cylindrical MOSFET structures, the proposed device shows reduced extrinsic parameters of the NQS model by 7.93% and 3.99% in C gde and C gse , respectively, and 33.4% and 23.9% in R D and R S . The revolutionary device's intrinsic gate‐drain capacitance ( C gd ) reduces by 7.13% and 4.29%, and its intrinsic gate‐source capacitance ( C gs ) reduces by 7.93% and 8.79% as compared to SB and SOISB cylindrical MOSFETs.