Degradation mechanisms and trap evolution in SiC asymmetric trench MOSFETs under power cycling tests

In this study, we investigated the degradation mechanisms of silicon carbide asymmetric trenches of metal-oxide semiconductor field-effect transistors (SiC AT-MOSFETs) under power cycling tests (PCTs). After 60000 cycles of PCTs with a heating current of 6 A, the threshold voltage increased by 7.1%, while the output saturation current decreased by 4.4%. Capacitance deep-level transient spectroscopy revealed two trap signals in the channel region: an electron trap at 100 K and a hole trap at 470 K, which moved to 190 and 420 K after the stress, respectively. In addition, an electron trap initially at 110 K in the junction field effect transistor (JFET) region changed to 210 K after the stress. An obvious decrease in gate–source capacitance after the stress further confirms that the primary degradation originates from the channel region, especially from the interface state electron trap (E1), rather than the JFET region. The positive shift in the threshold voltage and the decrease in the saturation current are attributed to the increased activation energy and density of this interface state, which inhibit the electron emission. These results provide new insights into the reliability of SiC AT-MOSFETs for high-voltage applications.