Modified Interleavers for Parallel Concatenated Block Codes with Flexible Lengths

The paper presents a modification of the interleaver used to construct Parallel Concatenated Block (PCB) codes with flexible lengths. This is accomplished for PCB codes whose interleaved message blocks have at most two bits of a message block. For this purpose, a two-step permutation is implemented, ensuring that the minimum weight of PCB codes has low multiplicity and is obtained from messages with weight one. Conducted analysis and simulations confirm that the new interleaver improves the performance of the PCB code (by 0.25 dB), which is evident at medium to high signal-to-noise ratios. Such improvement is evident for long-length PCB codes.