Implementation of Midori Cryptographic Algorithm Based on Chisel Language

In response to the issues associated with implementing cryptographic algorithms using the traditional hardware description language Verilog Hardware Description Language (Verilog HDL)—namely, high code complexity, long development cycles, and difficult debugging—this paper proposes a hardware implementation scheme for the lightweight block cipher algorithm Midori-128 based on the Chisel language. This scheme adopts an iterative structure and optimizes the algorithm for throughput. The algorithm has been successfully deployed on both Xilinx platforms and the domestically produced PGL100H platform, and a power consumption analysis has been completed. Compared to traditional Verilog implementations, this design delivers a throughput improvement of approximately 42.5% on the Virtex-5 platform and approximately 124.63% on the Spartan-6 platform. It maintains lightweight logic resource utilization and excellent cross-platform adaptability, making it suitable for resource-constrained embedded security applications and providing efficient, independently controllable cryptographic hardware support. Furthermore, the design fully preserves the symmetric cryptographic properties of Midori-128.