Runtime Approximate Computing in BioSoC Architectures for DNA Sequencing

In this work, we analyze the arithmetic building blocks of DNA basecalling to motivate runtime approximate computing in bio systems-on-chip (BioSoCs). We propose and characterize a reconfigurable compressor-tree multiplier whose operating mode can be selected at runtime to trade energy for controlled arithmetic error. Using a 45 nm CMOS evaluation flow, the proposed design demonstrates a clear power–accuracy trade-off across 64 operating modes, achieving about a 58–61% reduction in multiplier power (per multiply under fixed V/f) relative to an accurate Wallace baseline, with mean relative error distance (MRED) in the 1.05–2.88% range. At the application level, we outline a first-order noise-propagation model and, consistent with prior approximate-inference studies, note that task-level quality loss is often within a few percent (up to 5%), motivating end-to-end basecalling evaluation. Application-level evaluation on a TinyX3 DNA basecaller—a compact Bonito-based model—shows that the proposed multiplier with measured REV = 0.012 and MRED = 1.98% preserves near-baseline performance, with negligible degradation in sequence identity and relative length at low perturbation levels and only gradual accuracy decline (confirming ≤ 5% accuracy drop) emerging as perturbations increase into the moderate regime. Finally, a processor-level case study using convolution microbenchmarks (kernel footprints 9–49 weights per output) shows an 11% improvement in energy per instruction and a 12% reduction in energy per MAC when integrating the proposed multiplier into an embedded RISC-V execution engine.