Development of a reduced-switch nine-level inverter with low voltage stress for grid integration

Abstract Multilevel inverters have gained significant attention in medium-voltage and grid-connected applications due to their ability to generate high-quality output voltage with reduced harmonic distortion. However, conventional nine-level inverter topologies generally require a large number of power switches, capacitors, and voltage-balancing circuits, which increase system complexity and cost. This manuscript proposes a reduced-switch nine-level inverter topology based on the switched-capacitor technique to minimize component count while maintaining high-quality multilevel output. The proposed topology employs a modular structure and operates in both symmetrical and asymmetrical configurations, while inherent capacitor voltage balancing is achieved using a level-shifted pulse-width modulation scheme without requiring additional sensors or balancing circuits. Furthermore, 50 % of the power switches experience only 50 % of the total DC-link voltage stress, which improves device reliability and enables the use of lower-rated switches. The proposed inverter produces a high-quality nine-level output voltage with reduced component count and lower voltage stress compared with existing topologies. The feasibility and effectiveness of the proposed inverter are validated through MATLAB/Simulink simulations and experimental verification using a prototype hardware setup.