Gate dielectric stack design for 2D materials-based electronics

Abstract Two-dimensional (2D) semiconductors enable atomically thin channels and attractive electrostatics, but practical scaling increasingly hinges on gate-dielectric integration rather than channel performance. A key challenge is forming high-quality dielectrics on chemically inert, dangling-bond-free 2D surfaces while pushing equivalent oxide thickness to the sub-nanometer regime without excessive leakage, traps, or electrical breakdown. This review addresses the materials and process physics that govern dielectric formation in 2D devices, with an emphasis on atomic layer deposition nucleation, surface pretreatment and functionalization, and the use of seed and buffer layers for conformal high-κ oxides. The roles of layered insulators, such as hexagonal boron nitride, are discussed in terms of interface quality, electrostatic scaling limits, and transport limitations. The impact of dielectrics and processing on leakage mechanisms, defect generation, device-to-device variability, and reliability metrics, including time-dependent dielectric breakdown, bias-temperature instability, hysteresis, and threshold-voltage drift, is examined. Finally, we highlight van der Waals dry integration and dielectric transfer approaches that reduce process-induced damage and support wafer-scale uniformity, as well as opportunities for mixed-dimensional and 3D stacked architectures across logic, memory, and emerging functional systems. Graphical abstract