Event-Driven Analog-to-Digital Conversion: Precision-Adaptive Architectures and Continuous-Frequency Transforms

We present a continuous-time event-driven analogto-digital conversion framework in which signed amplitudeincrements are emitted at signal-determined instants rather thanon a uniform clock. The resulting reconstruction is a staircase withuniform amplitude error bounded by the elementary quantum ε.In the frequency domain, the derivative of the staircase is aweighted Dirac impulse train, yielding an exact continuousfrequencytransform evaluable at arbitrary frequencies withoutDFT binning. We then introduce the Horizontal Slice FourierTransform (HSFT), which decomposes the staircase into horizontalrectangular slices via a LIFO pairing rule and expresses eachslice as a closed-form sinc contribution. The method avoidsclassical uniform-sampling aliasing; its main spectral artifactis sinc side-lobe leakage, suppressed by a smooth Butterworthregularization window matched to the signal bandwidth. Timingjitter analysis shows that the 1/(j2πf) integration kernel cancelsthe frequency-dependent jitter penalty present in clockedconverters, yielding a frequency-flat noise floor with intra-sliceuncertainty σintra = εΔtq/√6, independent of signal frequencyby the Pythagorean identity. Performance metrics are derived: atequal maximum error, the PAN-ADC achieves the same SNR andENOB as a classical N-bit converter, without the direct frequencyproportionalENOB degradation of synchronous architectures. Thetimestamp clock records event times but does not drive conversion,making aliasing structurally absent. Numerical experiments on aJacobi–Anger test signal validate the time-domain error boundand the spectral framework. A second experiment on a 1024-QAM OFDM complex-baseband waveform shows that, under idealconditions, the PAN-ADC with threshold ε = q/4 and continuousfrequencydemodulation achieves EVM = −50.5 dB, satisfyingthe IEEE 802.11be specification of −47 dB in a configuratio