The Packaging Technology of CMOS Image Sensors: A Review

The CMOS image sensor (CIS) has been widely used in multiple fields such as smartphones, automotive electronics, security monitoring, and medical imaging. According to the structure, the CIS has usually been classified into front-side illumination (FSI) CIS, back-side illuminated (BSI) CIS, and stacked BSI CIS. The wafer-level packaging (WLP) technology based on the through-silicon via (TSV) for CIS chips mainly includes the laser drilling process, the flat stay process, and the ultrathin process, which have been developed by several outsourced semiconductor assembly and testing (OSAT) companies including SONY, Samsung Electronics, TSMC, Huatian Technology, and so on. Meanwhile, other advanced CIS packaging technologies including hybrid bonding, wafer-level stacking, and optical packaging technology have also been developed to meet the requirements of CIS chip packaging. The core pain points of CIS chip packaging including wafer warpage, thermal management, moisture reliability, and optical stray light also exist to prevent the development of CIS chip packaging. During the packaging process of CIS wafers, organic materials mainly including a cavity wall photoresist, high temperature bonding adhesive, printing ink, high transmittance adhesive, and photoresist were applied. The reliability testing of packaged CIS chips, including precon (including bake, soak, and reflow), high-temperature storage test (HTST), low-temperature storage test (LTST), temperature cycle test (TCT), and other tests, was performed to evaluate the reliability and durability of packaged chips by simulating various environmental conditions and stresses. Finally, the core challenges faced by technological upgrades for CMOS technology mainly included the physical limit approaching, the bottleneck of material system innovation, and the challenge of balancing performance and power consumption. The potential risks of CMOS technology in the field of security mainly included hardware-level vulnerabilities, security threats of the supply chain, and data security risks.

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Publication Details

Journal
ACS Applied Electronic Materials
Published
2026-04-28
DOI
https://doi.org/10.1021/acsaelm.6c00434
Primary Topic
3D IC and TSV technologies
Type
article
Field-Weighted Citation Impact
0.00

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article

The Packaging Technology of CMOS Image Sensors: A Review

Yue Wang, Jikang Liu
ACS Applied Electronic Materials
3D IC and TSV technologies
article

The Packaging Technology of CMOS Image Sensors: A Review

Yue Wang, Jikang Liu
article en

Abstract

The CMOS image sensor (CIS) has been widely used in multiple fields such as smartphones, automotive electronics, security monitoring, and medical imaging. According to the structure, the CIS has usually been classified into front-side illumination (FSI) CIS, back-side illuminated (BSI) CIS, and stacked BSI CIS. The wafer-level packaging (WLP) technology based on the through-silicon via (TSV) for CIS chips mainly includes the laser drilling process, the flat stay process, and the ultrathin process, which have been developed by several outsourced semiconductor assembly and testing (OSAT) companies including SONY, Samsung Electronics, TSMC, Huatian Technology, and so on. Meanwhile, other advanced CIS packaging technologies including hybrid bonding, wafer-level stacking, and optical packaging technology have also been developed to meet the requirements of CIS chip packaging. The core pain points of CIS chip packaging including wafer warpage, thermal management, moisture reliability, and optical stray light also exist to prevent the development of CIS chip packaging. During the packaging process of CIS wafers, organic materials mainly including a cavity wall photoresist, high temperature bonding adhesive, printing ink, high transmittance adhesive, and photoresist were applied. The reliability testing of packaged CIS chips, including precon (including bake, soak, and reflow), high-temperature storage test (HTST), low-temperature storage test (LTST), temperature cycle test (TCT), and other tests, was performed to evaluate the reliability and durability of packaged chips by simulating various environmental conditions and stresses. Finally, the core challenges faced by technological upgrades for CMOS technology mainly included the physical limit approaching, the bottleneck of material system innovation, and the challenge of balancing performance and power consumption. The potential risks of CMOS technology in the field of security mainly included hardware-level vulnerabilities, security threats of the supply chain, and data security risks.

ACS Applied Electronic Materials
Beijing Institute of Optoelectronic Technology (CN), Institute of Molecular Functional Materials (CN), Advanced Materials and Devices (United States) (US), Hubei University of Education (CN), Artificial Intelligence in Medicine (Canada) (CA)
Hubei Provincial Department of Education, Natural Science Foundation of Hubei Province, Hubei University of Education
Industry, innovation and infrastructure
Openalex Percentile: Top 7%
3D IC and TSV technologies
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