DSSZ-SM: A Simplified Chirp Coding Scheme with Inherent Clock Synchronization

This study proposes a novel double-slope chirp symbol, termed double–slope start zero stop minimum (DSSZ–SM), for efficient data communication. Unlike conventional chirp coding, which often involves complex generation and synchronization, the DSSZ–SM provides a simpler structure with inherent clock synchronization using a PWM-based generator. System performance is evaluated through analysis and simulations over additive white Gaussian noise (AWGN) and Rayleigh fading channels. Two asynchronous decoding methods, with and without an integrator, are compared. Results show that the non-integrator approach achieves lower error rates under both channel conditions. The proposed DSSZ–SM offers a simplified and robust alternative for efficient data communication. Keywords: Double-slope chirp, chirp encoding, asynchronous decoding, data communication