Impact of post-deposition annealing on the interface and electrical properties of ALD-deposited SiO2 and HfO2/SiO2 gate stacks on 4H-SiC MOS devices

This study investigates the influence of post-deposition annealing (PDA) ambient and temperature on atomic layer deposition (ALD)-grown SiO 2 and HfO 2 /SiO 2 gate dielectrics for 4H-silicon carbide (SiC) MOS devices. PDAs were conducted in either nitrogen (N 2 ) or forming gas (FG) environments over a temperature range of 600–1100 ° C . Comprehensive electrical characterization including capacitance–voltage (C–V), current–voltage (I–V), interface trap density ( D IT ), before implementing optimum PDA conditions in lateral MOSFETs. D IT values as low as ∼ 0 . 8 × 1 0 11 cm − 2 eV − 1 and 0 . 95 × 1 0 11 cm − 2 eV − 1 for ALD grown SiO 2 and HfO 2 /SiO 2 stacks. Lateral MOSFETs with the SiO 2 -only dielectric layer annealed in FG at 1100 ° C achieved a field-effect mobility of 33 . 93 ± 1 . 87 cm 2 /V s. In contrast, the same hydrogen-containing FG anneal had a deleterious effect on the HfO 2 /SiO 2 stacks; instead annealing the HfO 2 /SiO 2 layers in pure N 2 at 1100 ° C resulted in an increased mobility of 43 . 91 ± 2 . 07 cm 2 /V s. Grazing incidence X-ray diffraction (GI-XRD) confirmed that high-temperature annealing induces crystallization in the HfO 2 layer, while the SiO 2 layer remains amorphous. These findings emphasize the critical influence of PDA conditions and ambient atmospheres on dielectric quality, interface stability, and overall device performance for SiC-based MOSFETs. • Systematic PDA study of ALD SiO 2 and HfO 2 /SiO 2 gate stacks on 4H-SiC. • High-temperature PDA significantly reduces D it , V FB , and hysteresis. • Forming gas improves SiO 2 interfaces but degrades HfO 2 reliability. • N 2 annealing suppresses bulk HfO 2 defects and enhances dielectric strength. • HfO 2 /SiO 2 with N 2 PDA achieves μ FE up to 43.9 cm 2 /V s.