A 7.6-GHz Fractional-N Digital PLL with Time Amplifier-based Time-to-digital Converter

This paper presents a 7.6-GHz fractional-N digital phase-locked loop (DPLL) incorporating a time-amplifier (TA) based time-to-digital converter (TDC). The TA amplifies the phase residue and re-samples the loop counter, enabling fine time-to-digital conversion without significant hardware overhead. Because the TDC operates by counting the digitally controlled oscillator (DCO), its resolution automatically scales with the DCO period, eliminating the need for explicit gain matching, while an analog calibration compensates TA gain variation for robust PVT performance. For high-frequency capability, a latch-based counter is introduced, overcoming the operating-speed limitation of conventional synchronous counters. The PLL is implemented in 28-nm CMOS, the design occupies 0.027 mm², consumes 8.39 mW, and demonstrates ±0.5-LSB INL/DNL based on post-layout simulations, achieving 692-fs rms jitter at 7.693 GHz.