Ensuring Hardware Reliability and Security Using Terahertz <scp>VLSI</scp> ‐Based Tree Hierarchical Deep Convolutional Neural Network Testing Technology

ABSTRACT Hardware cyber security is a major issue in very large integrated circuits (ICs). The reliability and security of the system are vulnerable to counterfeit, forged, or defective ICs. The increasing complexity of digital and mixed‐signal systems makes it difficult to develop effective techniques for evaluating and validating the reliability of ICs. In this manuscript, ensuring hardware reliability and security using terahertz very‐large‐scale‐integration (VLSI)–based tree hierarchical deep convolutional neural network testing technology (EHRS‐TZ‐VLSI‐THCNN) is proposed. A focused terahertz laser is used to scan a radio frequency integrated circuit (RFIC), and the response on a single pin is evaluated to generate two dimensional (2D) pictures. The secure picture data set is created by a data augmentation technique to train the proposed algorithm. The proposed EHRS‐TZ‐VLSI‐THCNN approach achieves 25.26%, 31.74%, and 25.21% greater precision and 21.52%, 24.244%, and 25.65% better accuracy when compared to the existing models: AI‐powered terahertz VLSI testing technology to ensure hardware safety (CNN‐PT‐VLSI‐EHS), AI powered terahertz (THz) VLSI testing technology (PNDT‐PT‐VLSI‐EHS), and AI powered THz testing technology for ensuring hardware cybersecurity (AI‐PT‐VLSI‐EHS).

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Publication Details

Journal
Transactions on Emerging Telecommunications Technologies
Published
2026-04-26
DOI
https://doi.org/10.1002/ett.70403
Primary Topic
Physical Unclonable Functions (PUFs) and Hardware Security
Type
article
Field-Weighted Citation Impact
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article

Ensuring Hardware Reliability and Security Using Terahertz VLSI ‐Based Tree Hierarchical Deep Convolutional Neural Network Testing Technology

Nandakumar Easwaramoorthy, Jaya Jayabalan, Dharanika Thangamani
Transactions on Emerging Telecommunications Technologies
Physical Unclonable Functions (PUFs) and Hardware Security
article

Ensuring Hardware Reliability and Security Using Terahertz VLSI ‐Based Tree Hierarchical Deep Convolutional Neural Network Testing Technology

Nandakumar Easwaramoorthy, Jaya Jayabalan, Dharanika Thangamani
article en

Abstract

ABSTRACT Hardware cyber security is a major issue in very large integrated circuits (ICs). The reliability and security of the system are vulnerable to counterfeit, forged, or defective ICs. The increasing complexity of digital and mixed‐signal systems makes it difficult to develop effective techniques for evaluating and validating the reliability of ICs. In this manuscript, ensuring hardware reliability and security using terahertz very‐large‐scale‐integration (VLSI)–based tree hierarchical deep convolutional neural network testing technology (EHRS‐TZ‐VLSI‐THCNN) is proposed. A focused terahertz laser is used to scan a radio frequency integrated circuit (RFIC), and the response on a single pin is evaluated to generate two dimensional (2D) pictures. The secure picture data set is created by a data augmentation technique to train the proposed algorithm. The proposed EHRS‐TZ‐VLSI‐THCNN approach achieves 25.26%, 31.74%, and 25.21% greater precision and 21.52%, 24.244%, and 25.65% better accuracy when compared to the existing models: AI‐powered terahertz VLSI testing technology to ensure hardware safety (CNN‐PT‐VLSI‐EHS), AI powered terahertz (THz) VLSI testing technology (PNDT‐PT‐VLSI‐EHS), and AI powered THz testing technology for ensuring hardware cybersecurity (AI‐PT‐VLSI‐EHS).

Transactions on Emerging Telecommunications TechnologiesVol. 37(5)
Orthopaedic Research Group (IN), Hindustan Institute of Technology and Science (IN)
Openalex Percentile: Top 2%
Physical Unclonable Functions (PUFs) and Hardware Security
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