Design of electronically tunable fractional-order elements based on distributed MOS transistor structures

This paper presents a design algorithm and implementation results for electronically tunable fractional-order elements (FOEs) with capacitive character based on distributed MOS transistor structures compatible with standard CMOS technology. The proposed FOEs utilize the voltage-dependent resistive and capacitive properties of MOS transistors in the triode region, enabling continuous electronic tuning of the fractional order, or equivalently, the admittance phase, via external gate bias DC voltages. A synthesis methodology combining Simulated Annealing and gradient-based optimization is introduced to achieve constant-phase admittance responses over a wide frequency range for multiple target phases while preserving a fixed MOS-based topology. The approach is validated through numerical synthesis and measurements with samples fabricated in a 65 nm CMOS TSMC process. Experimental results demonstrate phase tunability of up to 10° over approximately three frequency decades and even up to 24° over two decades, with typical phase deviations within ± 1°. The presented MOS-based tunable FOEs provide a scalable integrated solution for implementing variable-order operators in analog signal processing, control, and modeling applications.