Automatic Layout Generation Strategies for Low-Power Standard Cell Design

With the rapid advancement of digital integrated circuits, transistor sizes and integration levels have grown at an unprecedented rate, leading to increasingly complex design processes. A key challenge in digital layout design is the placement and routing of standard cell circuit layouts, which directly impact chip quality and performance. Power is a critical factor in evaluating standard cells. To enable low-power standard cell layouts, the depth-first search (DFS) algorithm is proposed to model and place the standard cell. Additionally, the study aims to satisfy Design Rule Checking (DRC), a grid routing strategy based on the deep reinforcement learning (DRL) algorithm, which quickly identifies cell boundaries and barriers such as existing nets as well as contacts, while optimizing metal routing to achieve minimal power. Results show that the standard cell layouts generated by the DRL-based model achieve over a 90% reduction in design time and approximately 5% improvements in power compared with manual layouts. The proposed method facilitates the rapid development of standard cell library and has important engineering value.