DRR-NTT: Efficient NTT Accelerator in Lattice-Based Cryptography By Dimensionality Reduction in RRAM

Lattice-based cryptographic (LBC) algorithms, including Post-Quantum Cryptography (PQC) schemes and Fully Homomorphic Encryption (FHE), represent one of the most important families of quantum-resistant cryptosystems. A key computational primitive shared across these lattice-based algorithms is the Number Theoretic Transform (NTT), which often constitutes a performance bottleneck in practical implementations. Resistive random access memory (RRAM) is particularly well-suited for compute-in-memory (CIM) architectures due to its non-volatility, high density, analog computing capability, and inherent parallelism. Nevertheless, achieving high computational accuracy for NTT operations within RRAM-based CIM architectures remains a significant challenge for the efficient deployment of LBC.In this paper, we propose a novel NTT accelerator based on RRAM array, which is called DRR-NTT. First, we utilize a matrix decomposition method to create the most compact RRAM-CIM-based NTT architecture to date, which reduces system latency and significantly mitigates inter-column interference in the RRAM array. Second, we use a 3-bit weight mapping scheme for RRAM-based NTT accelerators, optimizing array utilization and accommodating various modulus values. Unlike prior works that relied solely on simulations, we incorporate real-world resistance measurements from fabricated RRAM devices into our quantization error analysis. Under equivalent conditions, our architecture achieves error control at the 10−6 level, surpassing previous CIM-based designs by over three orders of magnitude. Furthermore, we are the first to introduce the Plantard modular multiplication algorithm into RRAMbased CIM architectures, enhancing it to align with RRAM characteristics. This improvement boosts the efficiency of modular reduction operations while minimizing the hardware complexity and power consumption typically associated with managing precomputed twiddle factor matrices.Our architecture fully leverages the parallel nature of RRAM arrays and meets the high precision requirements of cryptography; it not only enhances throughput but also minimizes data movement overhead, leading to improved energy efficiency. Experimental results demonstrate that our proposed accelerator achieves a latency reduction of 1.5x ∼ 2.47x, an improvement in throughput and energy efficiency ranging from 1.6x ∼ 4.52x and over 1.5x improvement in throughput/area compared to state-of-the-art CIM-based solutions. This research will provide technical support for the efficient and high-precision implementation of LBC on RRAM.