Design of 16 × 16 Low-Timing-Jitter InGaAs/InP Single-Photon Avalanche Photodiode Array for LiDAR

The precise calibration of timing jitter in single-photon chips and LiDAR devices is critical for the development of high-precision LiDAR systems. This paper presents the design and fabrication of a double-diffused InGaAs/InP SAGCM single-photon avalanche diode (SPAD) with a timing jitter as low as 116 ps. Furthermore, a 16×16 InGaAs/InP array SPAD dToF readout circuit is implemented using a readout integrated circuit (ROIC) to interface the SPAD chip with an FPGA board. The array exhibits uniform distributions of photon detection efficiency (PDE) and dark count rate (DCR). However, the timing jitter of the array degrades significantly due to the timing resolution limitations of the time-to-digital converter (TDC) in the ROIC. To address this challenge, a novel timing jitter test method is proposed, which leads to substantial improvements. The array SPAD achieves a reduced timing jitter of 430 ps, a five-fold enhancement over results obtained with conventional methods. The findings of this study provide valuable insights for developing low-jitter InGaAs/InP SPAD arrays.

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Publication Details

Journal
IEEE photonics journal
Published
2026-04-22
DOI
https://doi.org/10.1109/jphot.2026.3686402
Primary Topic
Advanced Optical Sensing Technologies
Type
article
Field-Weighted Citation Impact
0.00

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article

Design of 16 × 16 Low-Timing-Jitter InGaAs/InP Single-Photon Avalanche Photodiode Array for LiDAR

Xing Wang, Linmeng Xu, Zefang Xu, Yu Chang et al.
IEEE photonics journal
Advanced Optical Sensing Technologies
article

Design of 16 × 16 Low-Timing-Jitter InGaAs/InP Single-Photon Avalanche Photodiode Array for LiDAR

Xing Wang, Linmeng Xu, Zefang Xu, Yu Chang, Ming Li, Fei Yin, Kai Qiao
article en

Abstract

The precise calibration of timing jitter in single-photon chips and LiDAR devices is critical for the development of high-precision LiDAR systems. This paper presents the design and fabrication of a double-diffused InGaAs/InP SAGCM single-photon avalanche diode (SPAD) with a timing jitter as low as 116 ps. Furthermore, a 16×16 InGaAs/InP array SPAD dToF readout circuit is implemented using a readout integrated circuit (ROIC) to interface the SPAD chip with an FPGA board. The array exhibits uniform distributions of photon detection efficiency (PDE) and dark count rate (DCR). However, the timing jitter of the array degrades significantly due to the timing resolution limitations of the time-to-digital converter (TDC) in the ROIC. To address this challenge, a novel timing jitter test method is proposed, which leads to substantial improvements. The array SPAD achieves a reduced timing jitter of 430 ps, a five-fold enhancement over results obtained with conventional methods. The findings of this study provide valuable insights for developing low-jitter InGaAs/InP SPAD arrays.

IEEE photonics journalVol. 18(3)
Xi'an Institute of Optics and Precision Mechanics (CN)
National Natural Science Foundation of China
Affordable and clean energy
Openalex Percentile: Top 15%
Advanced Optical Sensing Technologies
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