Hybrid Retransmission Architecture with Adaptive Bypass FEC Decoding for Low-Latency Lossless Networks

High-speed lossless networks widely adopt hybrid retransmission architecture at the link and physical layers to enhance the reliability of data transmission. However, the integration of Forward Error Correction (FEC) coding techniques introduces substantial latency, and existing configurable bypass error correction approaches struggle to adapt to the channel Bit Error Rate (BER) variability and granularity variations of transaction layer packets and FEC blocks. To address these challenges, this paper proposes a novel hybrid retransmission architecture, HARQ-apt, which optimizes data processing at the receiver side through a dual-path approach. Specifically, data is replicated into two paths after physical layer channel locking and reordering: one undergoes complete FEC decoding before entering the link layer, while the other bypasses FEC decoding entirely. The link layer identifies received packets using CRC and sequence numbers and employs the Go-Back-N mechanism to ensure reliable transmission of uncorrectable packets. The HARQ-apt architecture is implemented using RS(528,514) and RS(272,257) FEC coding for a 200Gbps high-speed lossless network design. Experimental results demonstrate that HARQ-apt achieves superior latency performance. ASIC (Application-Specific Integrated Circuit) synthesis using the FreePDK 45nm process shows that HARQ-apt incurs only marginal increases in hardware resources compared to traditional HARQ, with just 2.51% area overhead and 2.58% power overhead. Furthermore, FPGA (Field-Programmable Gate Array) prototype validation demonstrates its feasibility and effectiveness. These results highlight HARQ-apt as an efficient solution for high-speed data transmission, representing significant progress in addressing the challenges of FEC in high-speed networks, providing a practical approach for reliable, low-latency data transmission.

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Publication Details

Journal
Journal of Circuits Systems and Computers
Published
2026-04-22
DOI
https://doi.org/10.1142/s0218126626502233
Primary Topic
Interconnection Networks and Systems
Type
article
Field-Weighted Citation Impact
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article

Hybrid Retransmission Architecture with Adaptive Bypass FEC Decoding for Low-Latency Lossless Networks

Zongming Wu, Jijun Cao, Deyong Kong
Journal of Circuits Systems and Computers
Interconnection Networks and Systems
article

Hybrid Retransmission Architecture with Adaptive Bypass FEC Decoding for Low-Latency Lossless Networks

Zongming Wu, Jijun Cao, Deyong Kong
article en

Abstract

High-speed lossless networks widely adopt hybrid retransmission architecture at the link and physical layers to enhance the reliability of data transmission. However, the integration of Forward Error Correction (FEC) coding techniques introduces substantial latency, and existing configurable bypass error correction approaches struggle to adapt to the channel Bit Error Rate (BER) variability and granularity variations of transaction layer packets and FEC blocks. To address these challenges, this paper proposes a novel hybrid retransmission architecture, HARQ-apt, which optimizes data processing at the receiver side through a dual-path approach. Specifically, data is replicated into two paths after physical layer channel locking and reordering: one undergoes complete FEC decoding before entering the link layer, while the other bypasses FEC decoding entirely. The link layer identifies received packets using CRC and sequence numbers and employs the Go-Back-N mechanism to ensure reliable transmission of uncorrectable packets. The HARQ-apt architecture is implemented using RS(528,514) and RS(272,257) FEC coding for a 200Gbps high-speed lossless network design. Experimental results demonstrate that HARQ-apt achieves superior latency performance. ASIC (Application-Specific Integrated Circuit) synthesis using the FreePDK 45nm process shows that HARQ-apt incurs only marginal increases in hardware resources compared to traditional HARQ, with just 2.51% area overhead and 2.58% power overhead. Furthermore, FPGA (Field-Programmable Gate Array) prototype validation demonstrates its feasibility and effectiveness. These results highlight HARQ-apt as an efficient solution for high-speed data transmission, representing significant progress in addressing the challenges of FEC in high-speed networks, providing a practical approach for reliable, low-latency data transmission.

Journal of Circuits Systems and Computers
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Interconnection Networks and Systems
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