Emulation and mitigation of Multiple Bit Upset in SRAM memories using Interleaved Counter Matrix code

Multiple cell upsets are causing major problems with the reliability of memories exposed to radiation environments (MCUs). More complicated error correction codes (ECCs) are frequently employed to safeguard memory and stop MCUs from corrupting data, but their primary drawback is that increasing delay overhead is necessary. Recently, various ECC codes have been introduced however, the primary issue is that only two-to-five-bit errors are corrected faults can be corrected. To overcome these challenges, a novel Contiguous Multiple Bit Upset Mitigation (CMBUM) model has been proposed for data protection in SRAM memories. The proposed CMBUM model utilized Interleaved Counter Matrix (ICM) code which uses a combinational ones counter and parity generator to reduce delay overhead and improve memory reliability. CMBUM achieves maximal correction coverage by performing parallel 8-bit error correcting considerably. The proposed ICM code integrates the ICM code into the decoder and uses 32-bit data as input to the encoder in order to reduce the number of superfluous bits. The proposed method is implemented using a 45-nm library, and it is compared to the current approach, which provides better error protection with minimal redundancy and low overhead. Evaluation findings show notable reductions in area, power, and delay when comparing the proposed CMBUM technique to the existing technique, which can correct double and 8-adjacent faults.