Graphene-based interconnect exploration for FPGA design and optimization towards the end of the roadmap

The emerging graphene interconnect technology is expected to be a promising alternative to traditional interconnect technologies due to its superior conductivity. Because of the dominant impact of global routing on the overall performance of a widely used application, the Field-Programmable Gate Array (FPGA), this work investigates the potential advantage of using graphene-based interconnects to replace conventional copper (Cu) for global routing. Furthermore, a scalability analysis is performed, and the effects of technology node scaling from 7 nm to 1.5 nm are evaluated using lateral gate-all-around field-effect transistors (LGAAFETs) within the proposed system-technology co-design (STCO) framework. Key material-level parameters, including the mean free path (MFP), contact resistance, and the number of graphene layers, are systematically analyzed. Benchmark simulations demonstrate that a 32% improvement in the energy-delay product (EDP) is achieved with graphene-based interconnects compared to Cu counterparts at the 7 nm technology node, and an additional 46% reduction is observed at the 1.5 nm technology node. It is important to note that this work is an exploratory STCO study incorporating cross-layer design considerations, with a focus on long-term trends rather than short-term manufacturability.