Accelerating spiking neural networks with photonic reconfigurable devices

Spiking neural networks face hardware limitations as conventional architectures exhibit low array utilization, underperforming GPU-driven artificial neural networks in vision tasks. We present a programmable spiking neurocomputing architecture using CMOS-compatible photonic reconfigurable devices that unify synaptic/neuronal functions in single components. The optical isolation of photonic reconfigurable devices suppresses inter-cell crosstalk while enabling independent neuronal/synaptic programmability without operational redundancy. Programmable spiking neurocomputing architecture maximizes array utilization to enhance computational efficiency for spiking neural networks acceleration. Compared with conventional architectures, our architecture on spiking Visual Geometry Group networks demonstrates 1176× latency reduction and 239× energy savings in static recognition/classification and dynamic detection/tracking tasks, while maintaining equivalent recognition accuracy. This photonic-electronic integration establishes a scalable hardware framework that bridges the performance gap between spiking neural networks and state-of-the-art artificial neural networks, particularly for complex visual information processing applications requiring both efficiency and precision.