A 2-GS/s 35.9-fJ/conv.-step Voltage–Time Hybrid Pipelined ADC with Digital Background Calibration in 28-nm CMOS
. At 2 GS/s, the ADC achieves a Nyquist SNDR of 63.42 dB and an SFDR of 73.71 dB, corresponding to an ENOB of 10.24 bits. Consuming 86.9 mW from a 1-V supply, it achieves a Walden FoM of 35.9 fJ/conv.-step. Measurement results from multiple chips under a wide range of operating conditions verify the robustness of the proposed ADC.
Authors
- Yuan Chang (ORCID: https://orcid.org/0000-0002-9790-4529)
- Dongdong Chen (ORCID: https://orcid.org/0000-0002-5065-4374)
- Chaoyang Zhang (ORCID: https://orcid.org/0000-0003-3634-7324)
- Maliang Liu
- Yihang Yang
- Yintang Yang (ORCID: https://orcid.org/0000-0001-9745-5404)
- Chenghao Zhang
Institutions
- Xidian University (CN)
Publication Details
- Journal
- Micromachines
- Published
- 2026-04-17
- DOI
- https://doi.org/10.3390/mi17040495
- Primary Topic
- Analog and Mixed-Signal Circuit Design
- Type
- article
- Field-Weighted Citation Impact
- 0.00
Funders
- National Natural Science Foundation of China
- National Science and Technology Major Project