A 2-GS/s 35.9-fJ/conv.-step Voltage–Time Hybrid Pipelined ADC with Digital Background Calibration in 28-nm CMOS

. At 2 GS/s, the ADC achieves a Nyquist SNDR of 63.42 dB and an SFDR of 73.71 dB, corresponding to an ENOB of 10.24 bits. Consuming 86.9 mW from a 1-V supply, it achieves a Walden FoM of 35.9 fJ/conv.-step. Measurement results from multiple chips under a wide range of operating conditions verify the robustness of the proposed ADC.

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Publication Details

Journal
Micromachines
Published
2026-04-17
DOI
https://doi.org/10.3390/mi17040495
Primary Topic
Analog and Mixed-Signal Circuit Design
Type
article
Field-Weighted Citation Impact
0.00

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article

A 2-GS/s 35.9-fJ/conv.-step Voltage–Time Hybrid Pipelined ADC with Digital Background Calibration in 28-nm CMOS

Yuan Chang, Dongdong Chen, Chaoyang Zhang, Maliang Liu et al.
Micromachines
Analog and Mixed-Signal Circuit Design
article

A 2-GS/s 35.9-fJ/conv.-step Voltage–Time Hybrid Pipelined ADC with Digital Background Calibration in 28-nm CMOS

Yuan Chang, Dongdong Chen, Chaoyang Zhang, Maliang Liu, Yihang Yang, Yintang Yang, Chenghao Zhang
article en

Abstract

. At 2 GS/s, the ADC achieves a Nyquist SNDR of 63.42 dB and an SFDR of 73.71 dB, corresponding to an ENOB of 10.24 bits. Consuming 86.9 mW from a 1-V supply, it achieves a Walden FoM of 35.9 fJ/conv.-step. Measurement results from multiple chips under a wide range of operating conditions verify the robustness of the proposed ADC.

MicromachinesVol. 17(4)
Xidian University (CN)
National Natural Science Foundation of China, National Science and Technology Major Project
Affordable and clean energy
Openalex Percentile: Top 22%
Analog and Mixed-Signal Circuit Design
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