Topology-Aware Admission Control for Dynamic Load Balancing in NUMA-Based Parallel RTL Simulation

Parallel discrete-event simulation (PDES) of register-transfer-level (RTL) designs on multi-socket NUMA platforms demand dynamic load balancing to mitigate barrier-induced tail latency. However, the ultra-fine event granularity of RTL simulation makes migration cost non-negligible, and the non-uniform memory hierarchy of NUMA turns migration cost into a topology-dependent variable rather than a constant. Existing approaches either ignore this topology dependence or rely on heuristic thresholds that lack theoretical justification. This paper formulates NUMA-aware dynamic load balancing as a constrained optimization problem in which the migration cost is an explicit function of the socket locality between the source and destination cores. We introduce a unified net benefit function G(m,i→j,f) that jointly captures the tail-latency reduction, migration overhead, and cache warm-up penalty for migrating module m from core i to core j at frequency f. We prove that G is jointly concave in migration scale and frequency, yielding two analytical results: (i) a closed-form admission inequality that prescribes when migration is strictly beneficial, and (ii) a conservative fixed-frequency design rule that guides the choice of a global epoch length for the proposed epoch-based controller. We further show that when the initial static partition satisfies a bounded-quality condition, the total migration volume is provably bounded, formalizing the intuition that restraint is optimal, not merely conservative. We implement the proposed topology-aware admission control (TAC) framework in TACVS (Topology-Aware Admission Control Verilog Simulator), our event-driven parallel RTL simulation prototype. Experiments on four open-source RTL designs running on a 2-socket NUMA platform show that TAC reduces the tail-latency ratio by 18.0% on average (up to 28.5%) and improves normalized throughput by 27.1% on average (up to 34.1%) relative to topology-oblivious baselines. An ablation study further shows that admission control and cooldown are critical for performance, with throughput dropping by 15.9% and 22.8% on average (up to 22.4% and 32.5%) when each is removed, respectively.

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Publication Details

Journal
Electronics
Published
2026-04-16
DOI
https://doi.org/10.3390/electronics15081672
Primary Topic
Simulation Techniques and Applications
Type
article
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article

Topology-Aware Admission Control for Dynamic Load Balancing in NUMA-Based Parallel RTL Simulation

Zhaori Bi, Guangrong Li, X S Huang, Fan Yang
Electronics
Simulation Techniques and Applications
article

Topology-Aware Admission Control for Dynamic Load Balancing in NUMA-Based Parallel RTL Simulation

Zhaori Bi, Guangrong Li, X S Huang, Fan Yang
article en

Abstract

Parallel discrete-event simulation (PDES) of register-transfer-level (RTL) designs on multi-socket NUMA platforms demand dynamic load balancing to mitigate barrier-induced tail latency. However, the ultra-fine event granularity of RTL simulation makes migration cost non-negligible, and the non-uniform memory hierarchy of NUMA turns migration cost into a topology-dependent variable rather than a constant. Existing approaches either ignore this topology dependence or rely on heuristic thresholds that lack theoretical justification. This paper formulates NUMA-aware dynamic load balancing as a constrained optimization problem in which the migration cost is an explicit function of the socket locality between the source and destination cores. We introduce a unified net benefit function G(m,i→j,f) that jointly captures the tail-latency reduction, migration overhead, and cache warm-up penalty for migrating module m from core i to core j at frequency f. We prove that G is jointly concave in migration scale and frequency, yielding two analytical results: (i) a closed-form admission inequality that prescribes when migration is strictly beneficial, and (ii) a conservative fixed-frequency design rule that guides the choice of a global epoch length for the proposed epoch-based controller. We further show that when the initial static partition satisfies a bounded-quality condition, the total migration volume is provably bounded, formalizing the intuition that restraint is optimal, not merely conservative. We implement the proposed topology-aware admission control (TAC) framework in TACVS (Topology-Aware Admission Control Verilog Simulator), our event-driven parallel RTL simulation prototype. Experiments on four open-source RTL designs running on a 2-socket NUMA platform show that TAC reduces the tail-latency ratio by 18.0% on average (up to 28.5%) and improves normalized throughput by 27.1% on average (up to 34.1%) relative to topology-oblivious baselines. An ablation study further shows that admission control and cooldown are critical for performance, with throughput dropping by 15.9% and 22.8% on average (up to 22.4% and 32.5%) when each is removed, respectively.

ElectronicsVol. 15(8)
Fudan University (CN), Numerical Method (China) (CN), Institute of Applied Physics and Computational Mathematics (CN)
Reduced inequalities
Openalex Percentile: Top 9%
Simulation Techniques and Applications
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