A study on propagation delay and power dissipation of a 2-bit CMOS magnitude comparator with critical path evaluation

This work presents the design of 2-bit magnitude comparator in Cadence Virtuoso tool using gpdk090 technology. The detailed analysis of propagation delay and power dissipation (both dynamic and static power) for its outputs—L (A < B), E (A = B), and G (A > B) are analysed. The comparator was simulated and evaluated to quantify delay and power behaviour under varying conditions. Results show that the L (A<B) output achieves the shortest propagation delay of 7.55 ns, while the E (A=B) and G (A>B) outputs incur higher delays of 74.99 ns and 49.20 ns due to longer critical paths. Further, Results reveal that the L (A<B) output achieves the lowest power dissipation, with dynamic and static values of 5.07 mW and 1.49 µW, respectively, owing to its simple hierarchical decision path. The E (A=B) output exhibits the highest dynamic power consumption of 50.51 mW while maintaining a low static dissipation of 1.55 µW. This large dynamic overhead is attributed to the cascaded XNOR and AND logic used in equality detection, which introduces high switching activity and glitching effects. The G (A>B) output demonstrates moderate dynamic power of 8.11 mW but records the highest static leakage of 3.92 µW, arising from device sizing and threshold voltage trade-offs to enhance timing performance. These findings establish that equality detection is the most energy-intensive operation, while greater-than logic suffers from elevated leakage currents. The study provides critical insights into the relationship between logic structure and power characteristics, offering guidance for targeted low-power design strategies in comparator circuits and similar digital building blocks.