The Intelligent Wafer Bin Map Pattern Recognition Framework Integrating Attention-Based Deep Learning Network with Information Fusion

Currently, artificial intelligence (AI) applications and emerging technologies are driving the growing demand for silicon wafers. In complex semiconductor manufacturing environments, accurately recognizing failure patterns from defective wafers is crucial for yield improvement. This study develops an attention-based deep learning (DL) framework for wafer map pattern recognition (WMPR) by combining a DenseNet backbone with Subject Matter Expert (SME) knowledge. The proposed architecture comprises two complementary components: (i) an automatic feature learning module that integrates an attention mechanism to enhance spatial representation learning, and (ii) a manual feature generation module that injects interpretable SME-designed descriptors. To clarify the SME contribution, we explicitly define the manual descriptors as density-based distribution features, geometry-based region descriptors (rotation/scale invariant), and Radon-transform–based orientation descriptors, which jointly capture distribution-, morphology-, and orientation-level cues. In addition, connected-component labeling (CCL) is employed as a noise-aware preprocessing step to consolidate defect regions, and an 8-connected neighborhood is adopted to better preserve elongated structures (e.g., scratch-like patterns). Spatial pyramid pooling (SPP) is further incorporated at the input level to provide a fixedlength multi-scale representation for handling variations in wafer and die sizes. The deep representation and SME descriptors are fused and fed into a classifier to recognize defect types. To strengthen experimental rigor, we report comprehensive comparisons against representative WMPR baselines and present both module-level and feature-level ablation studies, including a w/o CCL variant to quantify the impact of CCL. We additionally provide a computational and runtime complexity analysis (Params, MACs/FLOPs, latency, and throughput) under a unified implementation setting, and use attention-map visualization to interpret spatial regions emphasized by the model. Experiments on real-world wafer map data demonstrate that the proposed framework achieves superior performance over prior approaches in terms of accuracy, precision, recall, and F1-score, while remaining practically deployable for WMPR in semiconductor manufacturing environments.