Crypto-Agile FPGA Architecture with Single-Cycle Switching for OFDM-Based Vehicular Networks

This paper presents a hardware-accelerated signal processing architecture for OFDM-based vehicular networks that integrates crypto-agile adaptive encryption on a Xilinx Kintex-7 FPGA. The encryption layer is tightly coupled to the OFDM modulation/demodulation pipeline, enabling secure real-time signal processing for V2X communications without disrupting the baseband chain. A context-aware pre-selection unit dynamically selects among hardware cipher primitives based on latency constraints, security requirements, and channel conditions. The current prototype implements and synthesizes AES-128 as the primary block cipher, while ASCON (NIST lightweight AEAD) and Keccak (SHA-3 foundation) are validated through RTL simulation and architectural integration, demonstrating crypto-agility across block, AEAD, and sponge-based primitives. DES is retained solely as a legacy reference for backward-compatibility evaluation and is not recommended for secure V2X deployment. The design adopts a modular decoupling strategy in which cryptographic engines interface with a unified buffering and interleaving subsystem, enabling hardware-based single-cycle cipher switching without partial reconfiguration. FPGA results demonstrate sub-microsecond cryptographic processing latencies with moderate resource utilization, preserving the timing budget of latency-sensitive vehicular services. AES-128 provides standard-strength encryption, while ASCON and Keccak offer lightweight and sponge-based alternatives suited to constrained IoV platforms. Specifically, the implemented AES-128 core achieves a throughput of 1.02 Gbps with a switching latency of 86 ns, verified across 10 randomized transitions with a 99.99% success rate and zero data corruption. The ASCON and Keccak cores attain throughput-to-area efficiencies of 2.01 and 1.47 Mbps/LUT, respectively, at a unified clock frequency of 50 MHz. All acronyms are defined at first use and a complete list of abbreviations is provided prior to the reference section.

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Publication Details

Journal
Signals
Published
2026-04-16
DOI
https://doi.org/10.3390/signals7020038
Primary Topic
Vehicular Ad Hoc Networks (VANETs)
Type
article
Field-Weighted Citation Impact
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article

Crypto-Agile FPGA Architecture with Single-Cycle Switching for OFDM-Based Vehicular Networks

Ahmed A. Ibrahim, Mahmoud Abdelaziz, mahmoud elomda
Signals
Vehicular Ad Hoc Networks (VANETs)
article

Crypto-Agile FPGA Architecture with Single-Cycle Switching for OFDM-Based Vehicular Networks

Ahmed A. Ibrahim, Mahmoud Abdelaziz, mahmoud elomda
article en

Abstract

This paper presents a hardware-accelerated signal processing architecture for OFDM-based vehicular networks that integrates crypto-agile adaptive encryption on a Xilinx Kintex-7 FPGA. The encryption layer is tightly coupled to the OFDM modulation/demodulation pipeline, enabling secure real-time signal processing for V2X communications without disrupting the baseband chain. A context-aware pre-selection unit dynamically selects among hardware cipher primitives based on latency constraints, security requirements, and channel conditions. The current prototype implements and synthesizes AES-128 as the primary block cipher, while ASCON (NIST lightweight AEAD) and Keccak (SHA-3 foundation) are validated through RTL simulation and architectural integration, demonstrating crypto-agility across block, AEAD, and sponge-based primitives. DES is retained solely as a legacy reference for backward-compatibility evaluation and is not recommended for secure V2X deployment. The design adopts a modular decoupling strategy in which cryptographic engines interface with a unified buffering and interleaving subsystem, enabling hardware-based single-cycle cipher switching without partial reconfiguration. FPGA results demonstrate sub-microsecond cryptographic processing latencies with moderate resource utilization, preserving the timing budget of latency-sensitive vehicular services. AES-128 provides standard-strength encryption, while ASCON and Keccak offer lightweight and sponge-based alternatives suited to constrained IoV platforms. Specifically, the implemented AES-128 core achieves a throughput of 1.02 Gbps with a switching latency of 86 ns, verified across 10 randomized transitions with a 99.99% success rate and zero data corruption. The ASCON and Keccak cores attain throughput-to-area efficiencies of 2.01 and 1.47 Mbps/LUT, respectively, at a unified clock frequency of 50 MHz. All acronyms are defined at first use and a complete list of abbreviations is provided prior to the reference section.

SignalsVol. 7(2)
Nahda University (EG), Military Technical College (EG), Minia University (EG)
Peace, Justice and strong institutions
Openalex Percentile: Top 23%
Vehicular Ad Hoc Networks (VANETs)
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