CORDIC‐Based Approximate Signed Multiplier With FPGA‐Aware Optimization

ABSTRACT Approximate computing has emerged as a promising paradigm for error‐tolerant applications, where accuracy can be leveraged to achieve performance improvements. Various compute‐ and memory‐intensive applications can benefit from the notion of using inaccurate computations with permissible variances to achieve performance improvements. This paper presents approximate signed multipliers based on the Coordinate Rotation Digital Computer (CORDIC) algorithm. By operating the CORDIC algorithm in the linear coordinate system using the rotation mode, the multiplication operation can be emulated. The simple add‐shift nature of the CORDIC algorithm eliminates the need for partial product generation and accumulation, leading to improved subsequent performance. A distinctive feature of the proposed designs is the systematic translation of the initial Boolean networks into a circuit netlist that optimally aligns with the coarse‐granular FPGA logic elements, viz., LUTs and Carry4 primitives. The accuracy‐versus‐performance trade‐offs of the proposed multipliers are validated in the context of two image processing applications, demonstrating their effectiveness in terms of the quality of the processed images.