Coordination of distance relays with a new flexible time-voltage-current characteristic numerical relay implemented using FPGA

• A flexible time-voltage-current characteristic (FTVCC) is proposed to enhance relay tripping time in power systems. • DS-FTVCC optimal coordination formulated as a nonlinear programming problem and solved using IPOPT and SCIP solvers. • Comprehensive analytical evaluation of standard and non-standard directional overcurrent relay curves against FTVCC. • Extensive case studies on IEEE 9-bus, 14-bus, and 39-bus benchmark test systems modelled in DIgSILENT PowerFactory. • FPGA-based semi hardware-in-the-loop validation is performed under both symmetrical and unsymmetrical fault cases. This paper delves into determining optimal zone-II settings for distance relays (DS) in coordination with numerical relays equipped with new proposed flexible time-voltage-current characteristics (FTVCC). A comprehensive comparative analysis is conducted, considering the existing standard and fully adjustable characteristic configurations of numerical relays proposed in the past literature on optimal protection coordination problem (OPCP). The study encompasses a thorough investigation of the applicability of the proposed FTVCC utilizing 9 bus, 14 bus, and IEEE 39 bus systems, with results compared across different relay characteristics. The results are achieved using nonlinear programming methodology with OPTI global optimization toolbox. The percentage reduction FTVCC achieved in the objective function is 41.09%, 37.72%, and 77.05% for the 9 bus, 14 bus, and IEEE 39 bus systems, respectively, when compared with the existing characteristics. The test systems are designed in DIGSILENT power factory, and the electromagnetic transient (EMT) simulations are extracted and fed to the FPGA-based FTVCCs through MATLAB Simulink interface in the experimental framework. This ensures that the performance and functionality of the proposed FTVCC are tested and verified under FPGA-validated conditions driven by different fault scenarios, serving as a preliminary semi-hardware verification step prior to full-scale field implementation for future works.